System for sequential synthesis and verification

https://people.eecs.berkeley.edu/~alanmi/abc/

Model generator for SPICE simulators

https://github.com/Qucs/ADMS

Open source ecosystem for open FPGA boards

https://github.com/FPGAwars/apio/wiki

Simple tool to analyze noise and distortion of a RF system

https://rfcascade.sourceforge.net/

Just-In-Time Compiler for Verilog from VMware Research

https://github.com/vmware/cascade

Digital logic designer and circuit simulator

https://github.com/hneemann/Digital

Driver for FTDI based JTAG probes, to program ECP5 FPGAs

https://github.com/gregdavill/ecpprog

FPGA assembly (FASM) parser and generator

https://github.com/SymbiFlow/fasm

FDM Material database for 3D printers

https://github.com/Ultimaker/fdm_materials

Finite element analysis program (personal version)

http://projects.ce.berkeley.edu/feap/feappv/

Easy to use graphical editor for electronics

https://darwinne.github.io/FidoCadJ/index.html

Application for rendering IC (chip) layouts in 3D

https://github.com/trilomix/GDS3D

C++ library to create and read GDSII file

https://github.com/judefdiv/gdscpp

GDS2 stream file to Postscript and HP/GL converter

C++ library for creation and manipulation of GDSII and OASIS files

https://heitzmann.github.io/gdstk/ https://github.com/heitzmann/gdstk/

Gerber file viewer

https://gerbv.github.io/

Fork of TimberWolf, a placement tool in VLSI design

https://github.com/rubund/graywolf

Electronic Waveform Viewer

https://gtkwave.sourceforge.net/

Dynamic Finite Element Program Suite

https://www.impact-fem.org/

Verilog simulation and synthesis tool

https://steveicarus.github.io/iverilog/

GUI control software for the stock K40 laser cutter controller

https://www.scorchworks.com/K40whisperer/k40whisperer.html

LDraw-format CAD files representing many of LEGO bricks produced

https://www.ldraw.org/

CAD program for creating virtual LEGO models

https://www.leocad.org/ https://github.com/leozide/leocad/

Implementation of the 3D Manufacturing Format file standard

http://3mf.io/

Prusa Block & Binary G-code reader/writer/converter

https://github.com/prusa3d/libbgcode

Library which provides a way to read/write CAD (DWG/DXF/DXFB) files

https://trac.osgeo.org/gdal/wiki/DWG_driver

2D CAD system

https://librecad.org/ https://github.com/LibreCAD/LibreCAD

Educational tool for designing and simulating logic circuits

http://ozark.hendrix.edu/~burch/logisim/

Interactive editor for VLSI layouts

http://opencircuitdesign.com/magic/

Tool for comparing netlists (a process known as LVS)

http://opencircuitdesign.com/netgen/

File format for compression of 3D triangle meshes

https://sourceforge.net/projects/openctm/

Universal utility for programming FPGA

https://github.com/trabucayre/openFPGALoader

GDS2 stream module

https://metacpan.org/release/GDS2

Building point for Verilog support in the Perl language

https://www.veripool.org/wiki/verilog-perl

Padring generator for ASICs

https://github.com/donn/padring

Coroutine based cosimulation library for writing VHDL and Verilog

https://www.cocotb.org/

Library for creation and manipulation of GDSII and OASIS files

https://heitzmann.github.io/gdstk/ https://github.com/heitzmann/gdstk/

Python VCD file support

https://pyvcd.readthedocs.io/en/latest/

GDSII manipulation library

https://pythonhosted.org/python-gdsii/

Professional CAD system

https://www.ribbonsoft.com/qcad.html

Tool to generate metal layers and vias

http://opencircuitdesign.com/qrouter/

Quite Universal Circuit Simulator: GUI for circuit simulation kernels

https://ra3xdh.github.io/ https://github.com/ra3xdh/qucs_s/

Circuit simulator of the Qucs project

https://github.com/Qucs/qucsator

Controller and GCode generator for RepRap 3D printers

https://reprap.org/wiki/RepSnapper_Manual:Introduction

GDSII reader and writer

http://rubyforge.org/projects/gdsii/

Generates C++ and Python from ISO10303 files

https://github.com/stepcode/stepcode/wiki

Traffic simulation suite for road vehicles, public transportation, etc

http://sumo-sim.org

SystemVerilog 2017 Pre-processor, Parser, Elaborator, etc

https://github.com/chipsalliance/Surelog

SystemVerilog linter

https://github.com/dalance/svlint

SystemVerilog language server

https://github.com/dalance/svls

Free interior 3D design application

https://www.sweethome3d.com/

SymbiYosys (sby): Front-end for Yosys-based formal verification flows

https://yosyshq.readthedocs.io/projects/sby/en/latest/ https://github.com/YosysHQ/sby/

Event driven digital circuit simulator

https://tkgate.org/

Free explicit/implicit Finite Element Program

https://tochnog.sourceforge.net/

Universal Hardware Data Model

https://github.com/chipsalliance/UHDM

Synthesizable Verilog to C++ compiler

https://www.veripool.org/projects/verilator/wiki/Intro

PCB (printed circuit board) design software

https://sourceforge.net/projects/veroroute/

X11 circuit schematics drawing program

http://opencircuitdesign.com/xcircuit/

Xyce electronic simulator

https://xyce.sandia.gov/

Compact Finite Element Analysis System

https://en.z88.de/